1. Field of the Invention
This invention relates in general to electronic circuits, and more particularly, to lateral silicon controlled rectifier (LSCR) structures for electro-static discharge (ESD) protection.
2. Description of the Prior Art
Electro-static discharge (ESD) is a significant problem in integrated circuit design, especially for devices with high pin counts and circuit speeds. ESD refers to the phenomena wherein a high-energy electrical discharge of current is produced at the input and/or output nodes of an integrated circuit (IC) device as a consequence of static charge build-up on the IC package. The static charge build up can result from handling of the IC device by a human body or from handling by IC device manufacturing equipments. It is known that the inadvertent presence of a sudden voltage spike in an integrated circuit can cause physical destruction of circuit features. For example, ESD-induced spikes can rupture the thin gate oxide of a field effect transistor (FET), or simply degrade the P-N junction of a semiconductor device, effectively destroying proper IC operation.
As well known in the art, lateral silicon controlled rectifier (LSCR) structures are widely used in the semiconductor integrated circuits to protect CMOS devices against high voltages during an ESD event. FIG. 1 is a schematic, cross-sectional view of a prior art LSCR structure 190. As shown in FIG. 1, LSCR structure 190 is formed in a P semiconductor layer 192 which is electrically contacted to cathode 62. An N well 194 is formed in P semiconductor layer 192. An N+ region 196 is formed in P semiconductor layer 192 and is electrically contacted to cathode 62. A P+ region 198 and an N+ region 200 are formed in N well 194 and are electrically contacted to anode 58. A field oxide region 202 is formed in N well 194, such that field oxide region 202 is interposed between P+ region 198 and N+ region 200. A thin gate oxide region 203 is formed over a region of P semiconductor layer 192 which is interposed between N+ region 196 and an N+ region 205. N+ region 205 is formed in P semiconductor layer 192 and in N well 194, such that N+ region 205 overlaps a junction 206 between P semiconductor layer 192 and N well 194. A polysilicon gate layer 207 is formed over gate oxide region 203 and is electrically contacted to cathode 62. A field oxide region 204 is interposed between P+ region 198 and N+ region 205.
FIG. 2 is a schematic, cross-sectional view of another prior art LSCR structure 220. As shown in FIG. 2, LSCR structure 220 may be formed on a P type epitaxial semiconductor layer 222. A lightly doped N well 224 is implanted in P semiconductor layer 222. After implanting N well 224 field oxide regions 232, 234, 238 and 240 are formed. A gate oxide region 233 is grown after the formation of the field oxide regions. Subsequently, a polysilicon gate layer 237 formed on the gate oxide region 233. An N+ region 226 and an N+ region 230 is then formed in P semiconductor layer 222, self-aligned to field oxide region 238 and gate oxide region 233, and self-aligned to field oxide regions 232 and 240, respectively. A P+ region 228 is formed in N well 224, self-aligned to field oxide regions 232 and 234.
The P semiconductor layer 222 is electrically contacted to cathode 62. N+ region 226 is electrically contacted to cathode 62. P+ region 228 and N+ region 230 are electrically contacted to anode 58. Field oxide region 232 is interposed between P+ region 228 and N+ region 230. Thin gate oxide region 233 is formed over regions of P semiconductor layer 222 and of N well 224 which are interposed between N+ region 226 and P+ region 228, such that gate oxide region 233 is formed over a junction 236 between P semiconductor layer 222 and N well 224. Polysilicon gate layer 237 is electrically contacted to cathode 62. Field oxide region 234 is interposed between gate oxide region 233 and P+ region 228. Polysilicon gate layer 237 extends over substantially all of gate oxide region 233 and over a portion of field oxide region 234.
However, the above-described LSCR structures have several shortcomings including lower efficiency and the need for larger chip area due to field oxide regions and/or N+ region between the field oxide region and the thin gate oxide region in the LSCR structures. Therefore, there is a need in this industry to provide an improved silicon controlled rectifier structure for electrostatic discharge protection, which is compatible with current CMOS processes, which has low threshold trigger voltages and improved efficiency, and which occupies relatively smaller chip areas. There is also a need for a simple IC structure that provides a low ESD trigger level reliably without extensive overhead circuitry and with an efficient use of IC space.